Digital Electronics MCQ

Digital electronics multiple choice questions provides mock tests for professional and competitive MCQ examinations by providing hundreds of multiple choice questions.

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RandomMCQ digital electronics MCQ covers topics on number systems, logic gates, combinational logic circuits, sequential logic circuits, memory, programmable devices, analog to digital and digital to analog converters.

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Digital Electronics
Intro to Digital Circits
Number Systems
Logic Gates
Combinational Circuits
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Digital Circuits

Intro to Digital Circuits

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Category: digital 1

Storage of 1 KB means the following number of bytes

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Category: digital 1

Positive logic in a logic circuit is one in which

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Category: digital 1

What is a  CORRECT statement

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Category: digital 1

Integrated-circuit counter chips are used in numerous applications including:

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NUMBER SYSTEMS

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The number of digits in octal system is

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Excess-3 code is known as

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In a positive logic system, logic state 1 corresponds to

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The chief reason why digital computers use complemented subtraction is that it

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The hexadecimal number for decimal  95.5  is

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The excess 3 code of decimal number 26 is

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1’s complement representation of decimal number of -17 by using 8 bit representation is

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The decimal equivalent of Binary number 11010 is

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Words having 8-bits are to be stored into computer memory. The number of lines required for
writing into memory are

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-8 is equal to signed binary number

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The code where all successive numbers differ from their preceding number by single bit is

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The 2’s complement of the number 1101101 is

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The Gray code for decimal number 6 is equivalent to

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The hexadecimal number ‘A0’ has the decimal value equivalent to

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The decimal equivalent of hex number 1A53 is

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What is the binary equivalent of the decimal number 368

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Convert decimal 153 to octal

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The decimal equivalent of binary 1100

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The binary equivalent of hexadecimal FA is

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The excess-3 code of decimal 7 is represented by

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The decimal equivalent of Binary number 10101 is

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The 2’s complement of the number 1101110 is

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The 1's complement of 1011000 is

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8723 in BCD equals

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The 2's complement of 1101100 is

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Gray code representation of 14 is

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The Bi-quinary code is the seven-bit code with

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The more convenient system for representing the negative numbers is

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Minterms whose sum defines Boolean function in a truth table are those that gives

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1's complement as a logical operation is equivalent to

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The 10's complement of 246700 is

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Convert decimal (153.513)to octal number system

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Gray code representation of 14 is

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842 + 537 is _______ in binary

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IF X=1010100 and Y=1000011,  using 2's complement X-Y is

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 Octal (16) in hexadecimal number system is equal to

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Using 10's complement subtracting 3250 from 72532 is equal to

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In which of the following base systems is 123 not a valid number?

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ASCII stands for

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How  is - represented with signed 2's complement?

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8620 in binary is

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Subtraction of two signed numbers is performed with

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A hexadecimal odometer displays F 52 F. The next reading will be

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What is the octal equivalent of the binary number:10111101

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In which of the following base systems is 123 not a valid number?

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A binary variable can take the values

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LOGIC GATES

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In case of OR gate, no matter what the number of inputs, a

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NAND. gates are preferred over others because these

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An OR gate has 6 inputs. The number of input words in its truth table are

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An AND gate will function as OR if

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Which of the following gate is a two-level logic gate

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The NOR gate output will be high if the two inputs are

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When the set of input data to an even parity generator is 0111, the output will be

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In a positive logic system, logic state 1 corresponds to

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How many AND gates are required to realize Y = CD+EF+G

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The NAND gate output will be low if the two inputs are

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How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB

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A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate?

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How many two-input AND and OR gates are required to realize Y=CD+EF+G

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NAND is a complement of

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2 binary terms x, y with AND operation give four possible combinations, representing these 4 terms in distinct areas in Venn Diagram is called

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 In digital logic design problems, x+x' is equal to

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if x=0, y=0, z=0, term x'y'z' in minterms have designation of

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A NAND gate is called a universal logic element because

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Which of the following gate is represented by x+y=z?

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Positive logic in a logic circuit is one in which

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NAND gate is called a universal logic element because

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The gates required to build a half adder are

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The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either

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Which of following are known as universal gates

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The logic 0 level of a CMOS logic device is approximately

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The exclusive-OR is an

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NOT gate is also known as

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COMBINATIONAL CIRCUITS

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Which segments of a CC seven-segment display would be required to be active to display the decimal digit 2?

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Integrated-circuit counter chips are used in numerous applications including:

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Which of following memory device requires refreshing

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The number of control lines for 16 to 1 multiplexer is

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How many address bits are required to represent a 32 K memory

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CMOS circuits consume power

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How many select lines will a 16 to 1 multiplexer will have

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How many AND gates are required to realize Y = CD+EF+G

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The A/D converter whose conversion time is independent of the number of bits is

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The access time of ROM using bipolar transistors is about

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The digital logic family which has the lowest propagation delay time is

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The gates required to build a half adder are

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The correction to be applied in decimal adder to the generated sum is

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The speed of conversion is maximum in

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How many select lines will a 32:1 multiplexer will have

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How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB

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A weighted resistor digital to analog converter using N bits requires a total of

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The conversation speed of an analog to digital converter is maximum with the following technique.

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The information in ROM is stored

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A full adder logic circuit will have

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Which of following can not be accessed randomly

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SSI stands for

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The number of control lines for 32 to 1 multiplexer is

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Sequential Circuits

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A counter with a modulus of 16 acts as a ________.

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Three cascaded decade counters will divide the input frequency by ________.

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The final output of a modulus-8 counter occurs one time for every ________.

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Which of the following is an invalid output state for an 8421 BCD counter

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How many different states does a 3-bit asynchronous counter have?

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A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

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How many flip-flops are required to construct a decade counter?

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The terminal count of a typical modulus-10 binary counter is ________.

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To operate correctly, starting a ring counter requires:

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A BCD counter is a ________.

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A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.

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When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers

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Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

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A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?

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Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

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How many flip-flops are required to make a MOD-32 binary counter?

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Shifting a register content to left by one bit position is equivalent to

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Which of following memory device requires refreshing

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How many flip flops are required to construct a decade counter

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A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The
maximum possible time required for change of state will be

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In a JK Flip-Flop, toggle means

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If the input to T-flipflop is 100 Hz signal, the final output of the three T-flip flops in cascade is

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A ring counter consisting of five Flip-Flops will have

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The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions

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An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately

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The output of SR flip flop when S=1, R=0 is

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For JK flip flop with J=1, K=0, the output after clock pulse will be

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